Day 23: Mat385

Today:

• Return Homework 6.3:
  • #3
  • #21

• Collect homework Section 6.4 homework and 7.1. homework

• Finish with Section 7.2: Logic Networks

  In particular we look at the half- and full-adder examples

• Section 7.3: Minimization

Next time: Review for test 2

Links:

• Maurice Karnaugh, The Map Method for Synthesis of Combinational Logic Circuits, Trans. AIEE. pt I, 72(9):593-599, November 1953.
• Karnaugh map according to NIST.
• Java applet to demonstrate Karnaugh
• Quine-McCluskey Logic Minimization (Java, in German!)
• Boolean Functions Simplification (Logic Minimization)
• Why carry-lookahead out-performs simple full adders:

  "The 4-bit adder we just created is called a ripple-carry adder. It gets that name because the carry bits "ripple" from one adder to the next. This implementation has the advantage of simplicity but the disadvantage of speed problems. In a real circuit, gates take time to switch states (the time is on the order of nanoseconds, but in high-speed computers nanoseconds matter). So 32-bit or 64-bit ripple-carry adders might take 100 to 200 nanoseconds to settle into their final sum because of carry ripple. For this reason, engineers have created more advanced adders called carry-lookahead adders. The number of gates required to implement carry-lookahead is large, but the settling time for the adder is much better."

• How electromagnets work
• How relays work
• Lecture about Quine McCluskey minimization